Static random access memory (SRAM) is used for cache memory because of its low power consumption and high operating speed compared to dynamic random access memory (DRAM). However, SRAM has a lower integration density than DRAM because the area occupied by a unit cell in an SRAM is greater than that in a DRAM. For example, an SRAM unit may normally be composed of six transistors, whereas a DRAM unit cell may only include one access transistor and a capacitor.
FIG. 1 illustrates a prior art SRAM unit cell which is composed of six transistors, PS1, PS2, LD1, LD2, PD1, PD2. Load transistors LD1 and LD2 are connected in series with drive transistors PD1 and PD2 respectively. The drive transistors PD1 and PD2 are arranged in a flip-flop or a latch type of arrangement. The sources of the load transistors LD1 and LD2 are connected to a power source Vcc, and the sources of the drive transistors PD1 and PD2 are connected to a ground voltage source Vs. The sources of the two transfer transistors PS1 and PS2 are connected to bit lines BL1 and BL2, and the gates of the two transfer transistors PS1 and PS2 are connected to a word line WL. The load transistors LD1 and LD2 may be replaced by load resistances.
A four-transistor loadless SRAM, in which load transistors LD1 and LD2 or equivalent load resistances are removed from the six-transistor SRAM structure, has been disclosed in U.S. Pat. No. 6,552,923, titled “SRAM WITH WRITE-BACK ON READ.” However, the loadless SRAM described therein uses a CMOS structure. More specifically, the transfer transistors are PMOSFET transistors, and the drive transistors are NMOSFET transistors. Thus, the loadless CMOS SRAM needs an isolation layer for isolating transfer transistors and drive transistors, and as a result, its integration density is limited. Furthermore, this loadless CMOS SRAM has a latch-up problem due to a well diode structure, and hence, it may need additional circuits to prevent the latch-up problem.
A loadless SRAM may maintain the voltage state of a storage node using the off-current of transfer transistors. However, since drive transistors also have an off-current, the node voltage may be unstable. Therefore, in order to increase the stand-by stability in a loadless SRAM, the off-current of the transfer transistors must be higher than the off-current of the drive transistors. However, since excessive off-current of the transistors may negatively influence device speed, switching characteristics and the like, it is necessary to control the off-current appropriately.